Semiconductor Integrated Circuits (IC) have Input/Output (I/O) pads that may be physically asymmetric, resulting in asymmetry between rise and fall times of passing signals.
FIG. 7 illustrates that in a conventional delta-sigma modulator circuit, when a Pulse-Density Modulated (PDM) signal passes through an asymmetric I/O pad and is demodulated or averaged using a Low Pass Filter (LPF), the asymmetry results in a Direct Current (DC) voltage offset. E1 and E0 represent the pulse widths of a logic 1 and of a logic 0, respectively. If the PDM signal passes through an I/O pad that is symmetric, the PDM signal rise and fall times are equal, and thus there is no DC voltage offset. On the other hand, if the PDM signal passes through an I/O pad that is asymmetric, there is a DC voltage offset, which may be positive or negative depending on the type of asymmetry. More specifically, if the rise time is less than the fall time, the DC voltage offset is positive. And if the rise time is greater than the fall time, the DC voltage offset is negative. DC voltage offset is not compensated for easily.
Conventional approaches for achieving symmetry between rise and fall times have focused on improving I/O pad design. Such approaches are disadvantageous in that they have longer design cycles, more complex pad designs, higher power consumption, larger area, and higher cost.